Vlsi Senior Engineer Sta - Bangalore - Aricent
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· Ability to work with juniors and guide them, if required.
· Manage own deliveries as defined in the project schedule
· Excellent verbal and written communication skills are required.
· Experience in synthesis of complex SoCs block/top level and writing timing constraints
· Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
· Experience in post-layout STA closure and timing ECOs
· Worked in technology nodes 45nm and below
· Knowledge of low-power aware implementation is a plus
STA, Timing Closure, ECO, Synthesis
Experience (In Month) : 70