19 May

Vlsi Senior Engineer Sta - Bangalore - Aricent

Position
Vlsi Senior Engineer Sta
Company
Aricent
Location
Bangalore KA
Opening
19 May, 2017 30+ days ago

Aricent as the company that open the jobs vacancy, have some qualification and spesification especially for the Vlsi Senior Engineer Sta jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Aricent company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

· Ability to work with juniors and guide them, if required.
· Manage own deliveries as defined in the project schedule
· Excellent verbal and written communication skills are required.
· Experience in synthesis of complex SoCs block/top level and writing timing constraints
· Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
· Experience in post-layout STA closure and timing ECOs
· Worked in technology nodes 45nm and below
· Knowledge of low-power aware implementation is a plus

MandatorySkills:
STA, Timing Closure, ECO, Synthesis

Experience (In Month) : 70

Qualification: BE


Other Vlsi Senior Engineer Sta Jobs Vacancy

23Jun

Senior Design Engineer. Job Openings in Chiptest for Senior Design Engineer, this job opened at 23 Jun, 2017. STA engineer to define timing constraints for DfT modes. M.Tech in Electronics, Electrical, VLSI. Engineer in silicon debug and pattern delivery for ATE.... ... (Read more about Senior Design Engineer - Chennai - Chiptest)


30Apr

Senior Engineer Design. Job Openings in Microchip Technology for Senior Engineer Design, this job opened at 30 Apr, 2017. BE/B.Tech/ME VLSI (EEE or ECE). A strong background in RTL level Digital IC Design using System Verilog/Verilog.... ... (Read more about Senior Engineer Design - - Microchip Technology)


19May

Vlsi Senior Engineer Sta. Job Openings in Aricent for Vlsi Senior Engineer Sta, this job opened at 19 May, 2017. STA, Timing Closure, ECO, Synthesis. Experience in post-layout STA closure and timing ECOs. Ability to work with juniors and guide them, if required.... ... (Read more about Vlsi Senior Engineer Sta - Bangalore - Aricent)


18May

Senior Engineer Rtl. Job Openings in Aricent for Senior Engineer Rtl, this job opened at 18 May, 2017. LEC & STA exposure desired. VLSI - SOC Integration and RTL design. Strong knowledge on digital & logic design · Hands-on experience with SoC RTL design &... ... (Read more about Senior Engineer Rtl - Bangalore - Aricent)


03May

Physical Design Engineer Senior. Job Openings in Whizchip Design Technologies for Physical Design Engineer Senior, this job opened at 03 May, 2017. Experience with Synopsys ICC tool for P&R, Synopsys Primetime tool for STA, Mentor Calibre tool for physical verification.... ... (Read more about Physical Design Engineer Senior - Bangalore - Whizchip Design Technologies)