19 May

Vlsi Engineer Sta - Bangalore - Aricent

Position
Vlsi Engineer Sta
Company
Aricent
Location
Bangalore KA
Opening
19 May, 2017 4 days ago

Aricent as the company that open the jobs vacancy, have some qualification and spesification especially for the Vlsi Engineer Sta jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Aricent company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

· Ability to work with juniors and guide them, if required.
· Manage own deliveries as defined in the project schedule
· Excellent verbal and written communication skills are required.
· Experience in synthesis of complex SoCs block/top level and writing timing constraints
· Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
· Experience in post-layout STA closure and timing ECOs
· Worked in technology nodes 45nm and below
· Knowledge of low-power aware implementation is a plus

MandatorySkills:
STA, Synthesis, Timing Closure, ECO

Experience (In Month) : 70

Qualification: BE


Other Vlsi Engineer Sta Jobs Vacancy

19May

Vlsi Engineer Sta. Job Openings in Aricent for Vlsi Engineer Sta, this job opened at 19 May, 2017. STA, Synthesis, Timing Closure, ECO. Experience in post-layout STA closure and timing ECOs. Ability to work with juniors and guide them, if required.... ... (Read more about Vlsi Engineer Sta - Bangalore - Aricent)


12Apr

Soc Lead Design Engineer. Job Openings in Intel for Soc Lead Design Engineer, this job opened at 12 Apr, 2017. B.Tech/M.Tech with 8+ years of experience in VLSI physical design activities. Should have the ability to technically lead a team of engineer to own execution... ... (Read more about Soc Lead Design Engineer - Bangalore - Intel)


10May

Soc Design Engineer. Job Openings in Intel for Soc Design Engineer, this job opened at 10 May, 2017. B.Tech/M.Tech with 6+ years of experience in VLSI physical design activities. Need familiarity of all back end sign-off activities like STA, LEC, CLP, EM/IR,... ... (Read more about Soc Design Engineer - Bangalore - Intel)


12Apr

Soc Physical Design Lead. Job Openings in Intel for Soc Physical Design Lead, this job opened at 12 Apr, 2017. B.Tech/M.Tech with 12+ years of experience in VLSI physical design activities. Should have the ability to technically lead a team of engineer to own execution... ... (Read more about Soc Physical Design Lead - Bangalore - Intel)


30Apr

Senior Engineer Design. Job Openings in Microchip Technology for Senior Engineer Design, this job opened at 30 Apr, 2017. BE/B.Tech/ME VLSI (EEE or ECE). A strong background in RTL level Digital IC Design using System Verilog/Verilog.... ... (Read more about Senior Engineer Design - - Microchip Technology)