17 Feb

Engineer - Pune - Seagate

Pune MH
17 Feb, 2017 30+ days ago

Seagate as the company that open the jobs vacancy, have some qualification and spesification especially for the Engineer jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Seagate company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

The candidate will work closely in a DI team for synthesis and STA of SoCs. The candidate will be responsible for following tasks.

  • Will be responsible for synthesis for hierarchical designs which includes feedback for RTL optimization and constraints clean-up.
  • Will be responsible for STA for hierarchical designs, recommending the timing closure methodology for a given STA sign-off. This STA involves multi-mode, multi-corner scenarios with OCV/AOCV/SI, what-if analysis, timing-ECO generation to fix timing/drc violations.
  • Hands-on usage and creation of ETM models used in Hard Macros.
  • Interface with physical design, IP team and RTL design team to debug timing issues and sign-off timing checks.

The candidate should be able to perform at least one of the following tasks.
  • IO timing closure for timing critical interfaces such as flash, PCIE and DDR.
  • Perform glitch analysis, SI analysis for interfaces such as DDR and flash.
  • Formal verification for the blocks.
  • Run power integrity checks for the design with UPF.

Must be technically adept, a strong team player and have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs. The candidate needs to have excellent interpersonal and communication skills and good problem solving skills.

The engineer should be at-least BE with 6 to 8 years of relevant VLSI experience in synthesis and STA. Strong individual contributors needed to support product line ASIC design. The candidate will work on leading edge storage solutions in an ASIC, full custom and SoC design.
  • The candidate should have demonstrated experience/exposure to synthesis and STA for high-speed digital designs.
  • Domain Expertise:
    • Synthesis for hierarchical designs with zero-wireload and physical.
    • Static Timing Analysis for hierarchical designs for functional and test modes with timing DRC fixes.
    • Experience in low power design and signal integrity.
    • Conversant about timing closure in physical design and timing-ECO generation.
    • Should have experience with formal verification and power analysis flow.
    • Technology node : 28nm / 40nm
    • Tools:
      • Synopsys: PrimeTime, Design Compiler Ultra, Formality, MVRC.
    • Interfaces
      • PCIE*
      • Flash controllers (ONFI*)
      • DDR2,3,4
      • GPIO
    • Expertise in scripting languages preferably Tcl.

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