Soc Design Engineer - Bangalore - Intel
Intel as the company that open the jobs vacancy, have some qualification and spesification especially for the Soc Design Engineer jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Intel company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.
Come join Intel's Scalable Performance CPU Development Group SDG as a SoC Design Engineer. General Duties: Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.Clock Specific Duties: This requisition is specific to clocking and hence the responsibilities would include the below. In this position, you will be responsible for SoC level clocking requirement definition, clock distribution planning and implementation of one or more of RTL to block level design execution/methodology which includes logic synthesis, auto place and route, extraction, low power design, static timing analyses/convergence, logical equivalence verification, quality & reliability convergence & layout verification using industry standard tools focused specifically on SoC level clock distribution. May involve working on Intel internal tools to build the clock network for simulation/convergence. Involve interaction with architecture and PLL design teams to define the clock requirements and clock distribution plans for the SoC. To be successful in this role, the candidate needs: - Strong communication skills verbal and written - Problem-solving skills - Ability to multitask - Strong teamwork skills and the capability of performing in a dynamic work environment - Ability to be flexible between multiple roles throughout the life of the project and continuously upgrading your skills.
Minimum Requirements Education: Bachelors/Masters in Electronics/Communication Engineering or related field with 8+ years of industry experience and proven track record in one or more of: Experience in SoC or IP/Macro level clock architecture & distribution and associated methodologies and in VLSI design flows and methods using industry standard/custom tools - Experience in scripting with unix shell, Perl/Tcl is added advantage Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.