17 Feb

Design Lead Staff Engineer - Bangalore - Connectpro Management Consultants Pvt Ltd

Position
Design Lead Staff Engineer
Company
Connectpro Management Consultants Pvt Ltd
Location
Bangalore KA
Opening
17 Feb, 2017 30+ days ago

Connectpro Management Consultants Pvt Ltd as the company that open the jobs vacancy, have some qualification and spesification especially for the Design Lead Staff Engineer jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Connectpro Management Consultants Pvt Ltd company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

SkillSet: physical design, device physics is essential.Candidate with hands -on experience. Technology Solutions Organization (TSO) which drives the technology developmentor maturity for production. You will be handling the SoC development for maturity certification of multiple collaterals like BISTor SRAM (SPor DPor HSor HD)or DDKor IOsor ROMor Efuseor on -chip/off -chip Process Monitoring IPs etc. in various technologies like C16FFor C40FGor C55FG etc.Your mission will be Driving Zero Defect physical design solution with best in class benchmark for Areaor Poweror Performanceor Quality and scheduleYour main duties will be: Defining the test -chip architectures and task distribution within the teamLeading physical design activities of complete test chipHandling the conference calls with the local or abroad teams for multiple engagements like project requirementsor schedule interlocks etcTracking the project status and making design deliveries with quality and schedule.We are looking for a candidate with these specific personal characteristic and qualificationsQualification: Candidate must possess skills to work on physical design of big SoC.

This includes but not limited to padring developmentor floor -planningor placementor routingor clock designor timing -optimizationor IR drop analysis and physical verification (DRC/LVS). Knowledge of all aspects of physical design and device physics is essential.Candidate with hands -on experience over cadence Rtl Compileror cadence SoC Encounteror Mentor Calibre DRC/LVSor apaches Redhawkor spice simulations would be preferred.Candidate should have very good communication and presentation skills.Masters in electrical/Electronics with special emphasis on VLSI design is desirable. (BE/B.Tech in Electrical/Electronics is a must)


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