Asic Design - Bangalore - Connectpro Management Consultants Pvt Ltd
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SkillSet: verification techniques like System Verilog, VMM, UVM. Experience in developing complex. Lead SoC integration and coordinate the design closure activities Work and interface with the customer leads to meet design goalsWork with STA leads for chip timing closure. Work with DfT leads for meeting test closure targets.Work with the Physical design team for design closure Work with IP teams to meet the SoC technical and delivery requirements.
Actively contributes to methodology and flow set -upor setting design targets (timingor poweror test) and work on improvements Contribute to gate -level simulations and debug. Technically lead/mentor team members. Contribute in audits/reviews and work with team and design manager to achieve timely and high quality deliverablesRequired knowledge and skills: VLSI Design flowsLogic and Circuit designExpertise in Verilog Worked on UPF/CPF based formal verification Worked on equivalence checksor Spyglass and constraint audit toolsSynthesis and PT - SI timing analysis for complex blocks and working through timing ECO fixes Worked on RTL and gate -level simulations and debug.Worked with multi clockor rail and high speed designs. Worked with multi -power domain designs and experience with low power methodologies and flows.
Worked with physical design team for timing closure.Very good communication skills Outstanding analytical and critical thinking skills.Desirable SkillsWorked on complex data path designs and/ IPsKnowledge of power analysis toolsExpertise in scripting languages Knowledge with timing analysis with multi voltage designs Worked with hierarchical flows Working knowledge of Physical design tools to aid timing closure