Engineer - Bangalore - Aricent
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Should be in VLSI Domain
Taking complete technical Ownership of full SoC RTL Design architecture.
Mentoring small 2 to 3 design RTL team.
Providing technical support to team and review of team technical delivery.
Completed ownership of SoC Chip level and Module Level Delivery from technical point of view on time along with 100% Quality.
Reviewing Spec document and providing feedback to customer.
VLSI, VHDL, Verilog and SV Hands on work experience. Full SoC Asic chip and Module level.
Experience (In Month) : 36
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