20 Mar

Prin Asic Design Engr - Bangalore - Cypress Semiconductor

Position
Prin Asic Design Engr
Company
Cypress Semiconductor
Location
Bangalore KA
Opening
20 Mar, 2017 7 days ago

Cypress Semiconductor as the company that open the jobs vacancy, have some qualification and spesification especially for the Prin Asic Design Engr jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Cypress Semiconductor company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

Job Overview

Join Cypress Semiconductor's IoT Team and develop WiFi MAC. This team is searching for a hands-on, team oriented verification engineer with a proven track record. In this role, the engineer will be responsible for leading verification of IoT WiFi IP. We are looking for a self-motivated and experienced engineer who can work with minimal supervision in our IP verification team and be able to work closely with our local and global design teams.

Job description

Leading Verification of IoT WiFi IP

Build and develop block level/system level test bench and simulation environment for WiFi MAC verification

Develop and execute thorough simulation and verification plan

Debug issues in RTL/gatelevel simulation

Participate in the emulation platform development and debugging

Be able to guide verification team

Debug issues in RTL/gatelevel simulation

Job Specific Requirement

BE/BTech Electrical/Electronic or ME/MTech in VLSI design

>10 yrs of Design Verification experience

Knowledge of digital communication systems and low power, high speed digital data path design is a plus

Familiarity with MAC implementation/verification of communication systems/protocols such as 802.11, LTE etc is a plus

Be proficient in Verilog/VHDL, be familiar with C/C++

ARM based SOC verification experience

Familiarity with AMBA - AXI,AHB,APB protocols is a plus

Strong verification skills like test planning, debug

At least one script language (TCL, Perl, Python and etc)

Proficiency in SystemVerilog, SystemC, UVM, and/or VMM

“Assertion based verification” knowledge

Familiarity with UPF/CPF based Verification flow and GLS

Good problem solving, communication and documentation skills

Experience

10-15yrs

Note

Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran


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